The SoC Baseband Processor Design For VLC

Abstract:
In this seminar, the design flow of Baseband Processor Design using System on Chip Technology will be discussed.  The SoC architecture is designed to optimally realize Visible Light Communication system.  Beside throughput, other aspects such as the design size, speed, real-time performance and design cost will be also considered.  The design flow includes the system design modeling, SoC architecture design, SoC Implementation, FPGA based prototyping and system verification.  An OFDM based SoC chip design is also presented. 

Biography:
Dr. Trio Adiono is an Assoc. Prof at the School of Electrical Engineering and Informatics of Institut Teknologi Bandung (ITB).  He obtained his Ph.D. degree in VLSI Design from Tokyo Institute of Technology (Titech), Japan. From 2002 to 2004 he was a research fellow of the Japan Society for the Promotion of Science (JSPS) in Titech. In 2005, he was a visiting scholar at MESA+, Twente University, Netherlands.  In 2006, he was a guest lecturer at University of Malaysia.  He currently also a Visiting Assoc. Prof at NTUST, Taiwan. He has published more than 160 papers and journals. He has developed several microchips, such as "Binary Template Matching Processor", Near Field Communication, and WiMax and IoT chip. Currently he is The Head of Microelectronics Center, Electronics Research Group and IC Design Laboratory-ITB.  His research interest are Chip Design, Broadband Wireless Communication, Near Field Communication and Visible Light Communication.